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seiko epson corporation 1 pf1005-02 E0C63B07 4-bit single chip microcomputer n description the E0C63B07 is a cmos 4-bit microcomputer composed of a cmos 4-bit core cpu, rom, ram, 7 segment type lcd driver, 10000 gates of gate array and counters. and the E0C63B07 can be operated by single manga- nese battery with lcd display. so that tha E0C63B07 is best suited for systems such as numeric pager. n features l cmos lsi 4-bit parallel processing l osc1 oscillation circuit ......................... 32.768/76.8/153.6khz (typ.) crystal oscillation circuit ( * 1) l osc3 oscillation circuit ......................... 400khz (max.) cr oscillation circuit, operatable in 0.9v l instruction set ........................................ basic instruction : 46 types (411 instructions with all) addressing mode : 8 types l instruction execution time ..................... during operation at 32.768khz : 61sec 122sec 183sec during operation at 76.8khz : 26sec 52sec 78sec during operation at 153.6khz : 13sec 26sec 39sec during operation at 400khz : 5sec 10sec 15sec l rom capacity ....................................... code rom: 8,192 words 13 bits l ram capacity ........................................ data memory : 1,024 words 4 bits display memory : 60 words 4 bits l input port ............................................... 8 bits (pull-up resistors may be supplemented * 1) l output port ............................................ 8 bits (it is possible to switch the 2 bits to special output * 2) l i/o port .................................................. 12 bits (it is possible to switch the 4 bits to serial input/output * 2) l serial interface ...................................... 1 port (8-bit clock synchronous system) l lcd driver ............................................. 60 segments 4, 3 or 2 commons ( * 2) 1/3 or 1/2 bias drive ( * 1) l time base counter ................................ 2 systems (clock timer, stopwatch timer) l programmable timer ............................. built-in, 2 inputs 8 bits, with event counter function l watchdog timer ..................................... built-in l gate array ............................................. sog : 10,000 gates number of terminals : 28 bits cpu interface : bus interface l melody generator .................................. equivalent to svm7100m series maximum 16 melodies melody rom capacity : 495 words (words can be optionally arranged for each melody) address control rom : 80 words (words can be optionally arranged for each melody) play output waveform : single sound square wave l supply voltage detection (svd) circuit .. 16 values, programmable (1.05v to 2.60v) l external interrupt .................................. input port interrupt : 2 systems l 4-bit low cycle / inst. core cpu l built-in 7 segment type lcd driver l low voltage operation (0.9v min.) l built-in gate array low voltage operation products
2 E0C63B07 l internal interrupt .................................... clock timer interrupt : 4 systems stopwatch timer interrupt : 2 systems programmable timer interrupt : 2 systems serial interface interrupt : 1 system gate array interrupt : 4 systems melody interrupt : 1 system l power supply voltage ............................ 0.9v to 3.6v l operating temperature range ............... -20 c to 70 c l current consumption (typ.) .................. single clock: during halt (32khz) 1.5v (normal mode, lcd power off) 1.2 m a 1.5v (normal mode, lcd power on) 2.0 m a 3.0v (halver mode, lcd power on) 1.5 m a during operation (32khz) 1.5v (normal mode, lcd power on) 6.0 m a 3.0v (halver mode, lcd power on) 3.5 m a twin clock: during operation (400khz) 3.0v (normal mode, lcd power on) 85 m a package .................................................... qfp8-160pin (plastic) or chip * 1: can be selected with mask option * 2: can be selected with software n block diagram osc1 osc2 osc3 osc4 com00?3(com10?3) seg0?9 v dd v c1 3 ca?d v d1 v d2 v ss mout r00?03 r10?13 k00?03 k10?13 test1 test2 reset p00?03 p10?13 p20?23 sc1 ?c28 core cpu e0c63000 rom 8,192 words 13 bits system reset control interrupt generator osc & prescaler ram 1,024 words 4 bits lcd driver 60 seg 4 com power controller svd melody generator output port stopwatch timer clock timer programmable timer/counter input port serial interface gate array block i/o port
3 E0C63B07 n pin configuration qfp8-160pin 81 120 41 80 index 40 1 160 121 E0C63B07 no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 no. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 no. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 no. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 name k10 n.c. k03 k02 k01 k00 n.c. n.c. n.c. n.c. n.c. ca cb cc cd v c3 v c2 v c1 v d2 v ss osc1 osc2 v d1 osc3 osc4 v dd reset test2 test1 mout p23 p22 p21 p20 p13 p12 p11 p10 n.c. n.c. name p03 p02 p01 p00 com13 com12 com11 com10 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 n.c. r00 name r01 r02 r03 r10 r11 r12 r13 sc1 sc2 sc3 sc4 sc5 sc6 sc7 sc8 sc9 sc10 sc11 sc12 sc13 sc14 sc15 sc16 sc17 sc18 sc19 sc20 sc21 sc22 sc23 sc24 sc25 sc26 sc27 sc28 n.c. n.c. n.c. n.c. n.c. name n.c. n.c. n.c. seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com03 com02 com01 com00 k13 k12 k11 n.c. : no connection
4 E0C63B07 n pin description signal name v dd v ss v d1 v d2 v c1 ? c3 ca, cb cc, cd osc1 osc2 osc3 osc4 k00?03 k10?13 p00?03 p10?13 p20?23 r00 r01 r02 r03 r10?13 com00?om03 com10?om13 seg0?eg59 mout sc1?c28 reset test1 test2 pin no. 26 20 23 19 18?6 12, 13 14, 15 21 22 24 25 6? 1, 160?58 44?1 38?5 34?1 80 81 82 83 84?7 157?54 48?5 153?24, 49?8 30 88?15 27 29 28 function power (+) supply power (? supply oscillation/internal logic system regulated voltage output supply voltage doubler/halver output lcd system power supply 1/3 or 1/2 bias (selected by mask option) lcd system boosting/reducing capacitor connecting supply voltage doubling/halving capacitor connecting crystal oscillation input crystal oscillation output cr oscillation input cr oscillation output input port input port i/o port i/o port (switching to serial i/f input/output is possible by software) i/o port output port output port output port (switching to tout output is possible by software) output port (switching to fout output is possible by software) output port lcd common output (1/4, 1/3, 1/2 duty can be selected by software) lcd segment output melody output g/a input/output initial reset input testing input testing input in/out i o i o i i i/o i/o i/o o o o o o o o o i, o, i/o i i i n electrical characteristics l absolute maximum ratings rating supply voltage input voltage (1) input voltage (2) permissible total output current * 1 operating temperature storage temperature soldering temperature / time permissible dissipation * 2 * 1: * 2: the permissible total output current is the sum total of the current (average current) that simultaneously flows from the outpu t pins (or is draw in). in case of plastic package (qfp8-160pin). symbol v dd v i v iosc s i vdd topr tstg tsol p d value -0.5 to 7.0 -0.5 to v dd + 0.3 -0.5 to v d1 + 0.3 10 -20 to 70 -65 to 150 260 c, 10sec (lead section) 250 unit v v v ma c c mw (v ss =0v) l recommended operating conditions condition supply voltage oscillation frequency symbol v dd f osc1 f osc3 remark v ss =0v doubler mode (osc3 off) doubler mode (osc3 on) normal mode (osc3 off) normal mode (osc3 on) halver mode (osc3 off) any one is selected duty 50 5%, vdc="1" unit v v v v v khz khz khz khz (ta=-20 to 70 c) max. 1.25 2.2 3.6 3.6 3.6 400 typ. 1.1 1.1 3.0 3.0 3.0 32.768 76.8 153.6 min. 0.9 0.9 1.25 2.2 2.5 50
5 E0C63B07 l dc characteristics unit v v v v a a a ma ma ma ma a a a a a a (unless otherwise specified: v dd =1.5v, v ss =0v, f osc1 =32.768khz, ta=25 c, v d1 /v c1 /v c2 /v c3 are internal voltage, c 1 ? 5 =0.2 f, c 6 ? 7 =0.4 f) max. v dd v dd 0.2? dd 0.1? dd 0.5 0 -3 -0.3 -0.3 -10 -10 -100 typ. -5 min. 0.8? dd 0.9? dd 0 0 0 -0.5 -8 0.7 0.7 10 10 100 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current low level input current (1) low level input current (2) high level output current (1) high level output current (2) low level output current (1) low level output current (2) common output current segment output current (during lcd output) segment output current (during dc output) symbol v ih1 v ih2 v il1 v il2 i ih i il1 i il2 i oh1 i oh2 i ol1 i ol2 i oh3 i ol3 i oh4 i ol4 i oh5 i ol5 v ih =1.5v v il1 =v ss no pull-up v il2 =v ss with pull-up v oh1 =0.9? dd v oh2 =0.9? dd v ol1 =0.1? dd v ol2 =0.1? dd v oh3 =v c3 -0.05v v ol3 =v ss +0.05v v oh4 =v c3 -0.05v v ol4 =v ss +0.05v v oh5 =0.9? dd v ol5 =0.1? dd condition k00?3, k10?3 p00?3, p10?3, p20?3 reset, test1, test2 k00?3, k10?3 p00?3, p10?3, p20?3 reset, test1, test2 k00?3, k10?3 p00?3, p10?3, p20?3 reset, test1, test2 k00?3, k10?3 p00?3, p10?3, p20?3 reset, test1, test2 k00?3, k10?3 p00?3, p10?3, p20?3 reset, test1, test2 r00?3, r10?3 p00?3, p10?3, p20?3 mout r00?3, r10?3 p00?3, p10?3, p20?3 bz com0?om3(10?3) seg0?eg59 seg0?eg59 unit v v v v a a a ma ma ma ma a a a a a a (unless otherwise specified: v dd =3.0v, v ss =0v, f osc1 =32.768khz, ta=25 c, v d1 /v c1 /v c2 /v c3 are internal voltage, c 1 ? 5 =0.2 f, c 6 ? 7 =0.4 f) max. v dd v dd 0.2? dd 0.1? dd 0.5 0 -6 -1.5 -1.5 -10 -10 -300 typ. -5 min. 0.8? dd 0.9? dd 0 0 0 -0.5 -16 6 6 10 10 300 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current low level input current (1) low level input current (2) high level output current (1) high level output current (2) low level output current (1) low level output current (2) common output current segment output current (during lcd output) segment output current (during dc output) symbol v ih1 v ih2 v il1 v il2 i ih i il1 i il2 i oh1 i oh2 i ol1 i ol2 i oh3 i ol3 i oh4 i ol4 i oh5 i ol5 v ih =3.0v v il1 =v ss no pull-up v il2 =v ss with pull-up v oh1 =0.9? dd v oh2 =0.9? dd v ol1 =0.1? dd v ol2 =0.1? dd v oh3 =v c3 -0.05v v ol3 =v ss +0.05v v oh4 =v c3 -0.05v v ol4 =v ss +0.05v v oh5 =0.9? dd v ol5 =0.1? dd condition k00?3, k10?3 p00?3, p10?3, p20?3 reset, test1, test2 k00?3, k10?3 p00?3, p10?3, p20?3 reset, test1, test2 k00?3, k10?3 p00?3, p10?3, p20?3 reset, test1, test2 k00?3, k10?3 p00?3, p10?3, p20?3 reset, test1, test2 k00?3, k10?3 p00?3, p10?3, p20?3 reset, test1, test2 r00?3, r10?3 p00?3, p10?3, p20?3 mout r00?3, r10?3 p00?3, p10?3, p20?3 bz com0?om3(10?3) seg0?eg59 seg0?eg59
6 E0C63B07 l analog circuit characteristics and current consumption * 1: no panel load. the svd circuit is off. unit v v v v v v v v v v v v v v v v v v v s a a a a a a a a a a a a a a a a a a a a a a a (unless otherwise specified: v dd =3.0v, v ss =0v, f osc1 =32.768khz, c g =25pf, ta=25 c, v d1 /v c1 ? c3 are internal voltage, c 1 ? 5 =0.2 f, c 6 ? 7 =0.4 f) max. 1.15 2? c1 +0.1 3? c1 +0.1 1.15 1.15 1.20 1.25 1.30 1.35 1.45 1.65 2.00 2.05 2.10 2.15 2.25 2.35 2.55 2.65 100 2.3 3.0 6.0 3.5 4.5 7.5 8.0 10.0 17.0 2.4 3.0 4.5 10.0 20.0 35.0 130.0 20.0 40.0 70.0 260.0 6.0 10.0 18.0 typ. 1.05 1.05 1.10 1.15 1.20 1.25 1.30 1.40 1.60 1.95 2.00 2.05 2.10 2.20 2.30 2.50 2.60 1.2 1.8 3.4 2.0 2.7 4.3 4.8 6.0 10.0 1.5 1.8 2.5 6.0 12.0 23.0 85.0 13.0 25.0 45.0 170.0 3.5 7.0 12.0 min. 0.95 2? c1 0.9 3? c1 0.9 0.95 1.05 1.10 1.15 1.20 1.25 1.35 1.55 1.90 1.95 2.00 2.05 2.15 2.25 2.45 2.55 characteristic lcd drive voltage svd voltage svd circuit response time current consumption symbol v c1 v c2 v c3 v svd t svd i op condition connect 1m w load resistor between v ss and v c1 (no panel load) connect 1m w load resistor between v ss and v c2 (no panel load) connect 1m w load resistor between v ss and v c3 (no panel load) svds0?="0" svds0?="1" svds0?="2" svds0?="3" svds0?="4" svds0?="5" svds0?="6" svds0?="7" svds0?="8" svds0?="9" svds0?="10" svds0?="11" svds0?="12" svds0?="13" svds0?="14" svds0?="15" during halt 32.768khz normal mode 76.8khz lcd power off 153.6khz during halt 32.768khz normal mode * 1 76.8khz lcd power on 153.6khz during halt 32.768khz doubler mode (v dd =1.2v) * 1 76.8khz lcd power on 153.6khz during halt 32.768khz halver mode (v dd =3.0v) * 1 76.8khz lcd power on 153.6khz during execution 32.768khz normal mode * 1 76.8khz lcd power on 153.6khz 400khz (cr oscillation) during execution 32.768khz doubler mode (v dd =1.2v) * 1 76.8khz lcd power on 153.6khz 400khz (cr oscillation) during execution 32.768khz halver mode (v dd =3.0v) * 1 76.8khz lcd power on 153.6khz
7 E0C63B07 l oscillation characteristics the oscillation characteristics change depending on the conditions (components used, board pattern, etc.). use the follow- ing characteristics as reference values. osc1 crystal oscillation circuit unit v v v pf ppm ppm ppm ppm ppm ppm v m w (unless otherwise specified: v dd =3.0v, v ss =0v, f osc1 =32.768khz, c g =25pf, c d =built-in, ta=25 c) max. 10 5 10 typ. 14 40 25 10 min. 1.1 1.1 0.9 -10 30 20 8 3.6 200 characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak condition t sta 3sec (v dd ) t stp 10sec (v dd ) including the parasitic capacity inside the ic (in chip) v dd =0.9 to 3.6v c g =5 to 25pf c g =5pf (v dd ) between osc1 and v dd , v ss normal mode doubler mode with vdc switching without vdc switching 32.768khz 76.8khz 153.6khz osc3 cr oscillation circuit unit % v v ms v v (unless otherwise specified: v dd =3.0v, v ss =0v, r cr =120k w , ta=25 c) max. 30 3 typ. 310khz min. -30 2.2 0.9 2.2 0.9 characteristic oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage symbol f osc3 vsta t sta vstp condition normal mode doubler mode v dd =2.2 to 3.6v ( doubler mode: v dd =0.9 to 2.2v ) normal mode doubler mode (v dd ) (v dd ) (v dd ) (v dd ) 10 100 cr oscillation resistance r cr [k w ] cr oscillation frequency f osc3 [khz] 1000 100 1000 10000 10 v dd = 2.2 to 3.6 v (normal mode) v dd = 0.9 to 2.2 v (doubler mode) v ss = 0 v ta = 25 c typ. value cr oscillation frequency-resistance characteristics
8 E0C63B07 l serial interface ac characteristics clock synchronous master mode (during 32 khz operation) unit s s s (condition: v dd =1.5v, v ss =0v, ta=25 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd ) max. 5 typ. min. 10 5 characteristic transmitting data output delay time receiving data input set-up time receiving data input hold time symbol t smd t sms t smh clock synchronous master mode (during 400 khz operation) unit ns ns ns (condition: v dd =3.0v, v ss =0v, ta=25 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd ) max. 200 typ. min. 400 200 characteristic transmitting data output delay time receiving data input set-up time receiving data input hold time symbol t smd t sms t smh clock synchronous slave mode (during 32 khz operation) unit s s s (condition: v dd =1.5v, v ss =0v, ta=25 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd ) max. 10 typ. min. 10 5 characteristic transmitting data output delay time receiving data input set-up time receiving data input hold time symbol t ssd t sss t ssh clock synchronous slave mode (during 400 khz operation) unit ns ns ns (condition: v dd =3.0v, v ss =0v, ta=25 c, v ih1 =0.8v dd , v il1 =0.2v dd , v oh =0.8v dd , v ol =0.2v dd ) max. 500 typ. min. 400 200 characteristic transmitting data output delay time receiving data input set-up time receiving data input hold time symbol t ssd t sss t ssh master mode sclk out sout sin v oh v oh v ol t sms t smh t smd v ih1 v il1 v ol slave mode sclk in sout sin v ih1 v oh v ol t sss t ssh t ssd v ih1 v il1 v il1
9 E0C63B07 l melody generator ac characteristics * 1 the quantization error becomes smaller than the standard value about by synchronization with the external clock. therefore, actual time t is as follows: (standard value - external clock 1 cycle ) < t < standard value) unit ms s s s s ms ms ms sec sec sec sec (unless otherwise specified: v dd =3.0v, v ss =0v, ta=25 c) max. 31.25 * 1 1.68 1.96 1 beat 2 beats note length at change typ. min. 27.4 * 1 10 10 10 10 0.0039 1 beat 1 beat 1 beat 0 characteristic play start mt minimum pulse width frequency selection data set-up time melody selection data set-up time melody selection data hold time play mode selection data set-up time play start delay time output inverting time play suspension time (1) play suspension time (2) mt=0 minimum pulse width mt=1 minimum pulse width melody changing time during play symbol t on1 t sck t sms t hms t spm t b t out t e1 t e2 t off t on2 t mc condition "melody change during play is impossible" option f osc1 =76.8, 153.6 khz f osc1 =32.768 khz "melody change during play is possible" option play start timing mt f osc1 cksn msn pmn play control (mply register) mout t on1 t sck t sms t hms t spm t b t out clock frequency selection melody selection play mode selection play melody and play mode selections should be done before starting the play (before setting the mt register to "1"), though it is no problem if the set- up time can be maintained. play stop timing ? level hold play and one-shot c play ? start/stop control by mt mt mout t e1 mt mout t e2 t off t on2 change of melody during playing ? when the mask option "possible to change" is selected msn (melody selection) play output t mc melody y melody x first note in melody y melody x
10 E0C63B07 l timing chart initial reset supply voltage osc1 oscillation clock oscillation detection circuit output reset terminal internal reset signal (note) f osc1 =32.768 khz f osc1 =76.8 khz f osc1 =153.6 khz : 6 msec min. : 3 msec min. : 1.5 msec min. 3 sec (high active) (low active) (high active) (note) oscillation is in unstabilized state system clock switching dbon (note) vdsel (note) vdc oscc clkchg (note) use dbon and vdsel only when changes are requied. * * * * 100 msec min. * 2.5 msec min. 5 msec min. * 1 instruction execution time or longer supply voltage doubler control during heavy load driving dbon vdsel vcsel (note) heavy load on off (note) vcsel is used only when it is required. * * 100 msec min. 100 msec min. 1 msec min. 2 sec min. * 1 instruction execution time or longer
11 E0C63B07 n basic external connection diagram note: the above table is simply an example, and is not guaranteed to work. ca cb cc cd v v v dd d1 d2 osc1 osc2 osc3 osc4 reset v ss c 6 c 2 c 7 c gx c res c p 0.9 v | 3.6 v + x'tal k00?03 k10?13 p00?03 p10 (sin) p11 (sout) p12 (sclk) p13 (srdy) p20?23 r00 r01 r02 (tout) r03 (fout) r10?13 sc1?c28 seg0 | seg59 com00 (10) | com03 (13) c 3 c 4 c 5 test2 test1 c 1 v v v c1 c2 c3 mout piezo coil input i/o i/o output lcd panel 60 4 E0C63B07 [the potential of the substrate (back of the chip) is v ss .] r cr x'tal c gx r cr c 1 ? 5 c 6 , c 7 c p crystal oscillator trimmer capacitor resistor for cr oscillation capacitor capacitor capacitor 32.768 khz/76.8 khz/153.6 khz, c i (max.) = 34 k w 5?5 pf 120 k w (max. 400 khz) 0.2 f 0.4 f 3.3 f
E0C63B07 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade control law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 1999 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110

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